Indian Journal of Science and Technology
DOI: 10.17485/ijst/2018/v11i6/117898
Year: 2018, Volume: 11, Issue: 6, Pages: 1-6
Original Article
Huan Minh Vo1 and Quoc Ai Dao2
1 Ho Chi Minh University of Technology and Education, Vietnam; [email protected]
2 National Chung Cheng University, Taiwan; [email protected]
*Author for correspondence
Huan Minh Vo,
Ho Chi Minh University of Technology and Education, Vietnam; [email protected]
Objectives: To innovate power gating technique which is used to recycle charge lost at moment from active to sleep mode by both PMOS header and NMOS footer. Methods: Three 32-bit Carry Look Ahead (CLA) adder circuits and ISCAS-85 benchmark circuits are compared in retention mode including the conventional power gating, single recycled charge power gating, dual recycled charge power gating in term of the power consumption using the 45 nm Predictive Technology Model. A fair timing comparison also is considered in this work. Findings: This proposed 32-bit CLA adder can reduce the standby leakage power consumption up to 60% and 53% in short and long sleep time, respectively, compared to the conventional power gating. Compared to the single recycled charge, the proposed saves up to 25% in short sleep time and 44% in long sleep time. The proposed 32-bit CLA adder is simpler in controlling the circuit in active mode and retention mode. The ISCAS-85 benchmark circuits are also applied to make conclusion in term of saving leakage power consumption. Application: This proposed leakage reduction technique is promising candidate for optimizing more leakage dissipation in digital circuits.
Keywords: Charge Recycling, CLA Adder, Leakage Current, Low Power, Power Gating
Subscribe now for latest articles and news.
