• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 34, Pages: 1-6

Original Article

FPGA Specific Real Time Hardware Architecture Implementing Bounding Box Merging Algorithm for Object Detection


Objectives: This paper focuses on the real time hardware implementation of improved version of Viola Jones algorithm for automatic object detection. Methods/Statistical Analysis: In this regard, A greedy NMS(Non Maximum Suppression) approach has been adopted to develop the bounding box merging algorithm which could suppress the confusing dense grid of overlapping bounding boxes against a threshold value and gives an accurate result and further this algorithm has been transformed in to a real time hardware architecture. Findings: The hardware architecture designed is fully Field Programmable Gate Array (FPGA) based which will take the input coordinates of the image and will process it accordingly by reducing the number of overlapped bounding boxes in real time. Applications/Improvements: Any researcher who is working on automatic object detection can use this hardware architecture as it is in his design and further this architecture itself can be used to create Application Specific IC (ASIC).
Keywords: Bounding Box, Field Programmable Gate Array (FPGA), Non Maximum Suppression (NMS), Non-Maximum Suppression Finite State Machine (NMS-FSM), Real Time, Video Graphics Array (VGA)


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