High Performance FIFO Design for Processor through Voltage Scaling Technique

Abhay Saxena; Ashutosh Bhatt; Parth Gautam; Puneet Verma  and Chandrashekhar Patel

doi:10.17485/ijst/2016/v9i46/106916

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High Performance FIFO Design for Processor through Voltage Scaling Technique

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2016/v9i46/106916

Year: 2016, Volume: 9, Issue: 46, Pages: 1-8

Original Article

High Performance FIFO Design for Processor through Voltage Scaling Technique

Abhay Saxena¹ , Ashutosh Bhatt² , Parth Gautam¹, Puneet Verma³ and Chandrashekhar Patel¹

¹Dev Sanskriti Vishwa Vidayalaya, Haridwar, Uttarakhand-249411, India; [email protected], [email protected], [email protected] ²Department of Computer Science, BIAS, Bhimtal, Uttarakhand-263136, India; [email protected] ³Department of Computer Science, SIT, Pithoragarh, India; [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Green computing is making revolution by bringing high speed processor with less power consumption. Our paper is based on this philosophy. Objectives: To come out High Performance FIFO for processor by minimizing the power consumption. Methods/Statistical Analysis: To make FPGA based design of FIFO we used voltages and frequency scaling techniques. Keeping voltage constant at 2.3 volt we varied frequency from 20MHz to 250MHz and for other experiment we kept the frequency constant and varies voltages from 1volt to 2.3 volt. Findings: The power consumption is reduced to 95.79% on voltage scaling where as there is a 4.38% less power consumption on frequency scaling. Application/Improvements: It will surely help in futuristic processor development.

Keywords: Field Programmable Gate Array (FPGA), First in First Out (FIFO), Hardware Description Language (HDL), High Performance Design, Voltage Scaling