Indian Journal of Science and Technology

Abstract

Background: Discrete Wavelet Transform (DWT) is extensively useful in different Digital Signal Processing (DSP) applications. In this paper, Lifting scheme is introduced in three mother wavelets, which are Haar wavelet, Daubechies (db4) and Cohen-Daubechies-Feauveau (CDF) 9/7-tap wavelet also known as db9/7 wavelet. Method: In this work each of the architecture is compared with its Direct form. Haar wavelet is used to design the basic DWT architecture. Daubechies DWT (db4) orthogonal filters and Cohen-Daubechies-Feauveau (CDF) 9/7 bi-orthogonal wavelet filters are considered for DWT construction. Due to the uncomplicated design, lifting scheme provides less power consumption. Instead of set of filters, simple predict and update mechanism is introduced. The IEEE 754 floating point standard is used to represent the filter coefficients. The architectures are described in Verilog HDL and simulation is performed in Xilinx for FPGA implementation. All the architectures are synthesized in Cadence RC for 180 nm technology. Findings: The Lifting Scheme has 75-82% less power consumption and 27% area-efficiency than conventional DWT architectures. FPGA implementation is done using Altera Cyclone IV FPGA kit. Maximum operating frequency is 33.3MHz and 45MHz for 3-level and 1-level of decomposition respectively in DWT implementation. Conclusion: Due to the uncomplicated design, lifting scheme provides less power consumption. DWT designs are compared with respect to power consumption and area.
Keywords: Cohen-Daubechies-Feauveau (CDF) 9/7 wavelet, Daubechies Wavelet (db4), Discrete Wavelet Transform (DWT), Lifting Scheme