Indian Journal of Science and Technology

Abstract

Cache memories are revealed to transitory error in tag bits and some of the efforts have been taken to decrease their susceptibility. In the advanced mechanisms of cache memories are most applicable components, because the soft errors are protected. The identical tag bit data is used to regain from the error in the tag bits. In this paper, to improve error protection capacity of the tag bits in caches, power efficient cache design is proposed by using Superlative Standard Techniques (SST) architecture to achieve power. To utilize the identical tag bits for transitory error protection, the proposed scheme is discussed by selecting the energy superlative standard techniques that decrease unwanted interior activities by reducing the dynamic switching power. In experimental method, results show that our proposed multilevel cache architecture sustains a performance of achieving dynamic power and reduces the power consumption up to 85% when applied to energy optimal technique.
Keywords: Cache Memories, Identical Tag Information, Superlative Standard Techniques (SST), Tag Bits, Transitory Error