Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 10, Pages: 1-8
Kavita Goswami1 *, Bishwajeet Pandey2 , D. M. Akbar Hussaian3 , Tanesh Kumar4 and Kartik Kalia1
1Gyancity Research Lab, South City-1 Enclave, Gurgaon - 122001, Haryana, India; [email protected]. com,[email protected] 2GSSI, Italy; [email protected] 3Aalborg University, Denmark; [email protected] 4University of Oulu, Finland; [email protected]
*Author for Correspondence
Kavita Goswami Gyancity Research Lab, South City-1 Enclave, Gurgaon - 122001, Haryana, India; [email protected]. com
Multiplier is used for multiplication of a signal and a constant in Digital Signal Processing (DSP). 28nm technology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and XpowerAnalyser. Vedic multiplier gains speed improvements by parallelizing the generation of partial products with their concurrent summations. In this work, we are exploring the feasibility of Vedic multiplier in Data Encryption Algorithm, DSP, reliable system, multimedia and fault tolerant systems. In our work, we are using 11 different IO standards from HSTL (High Speed Transistor Logic) and LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor) family. IO standards are used to match the impedance of transmission line, input/output port and device. The energy-efficient multipliers play a significant role in portable computing and communication systems also. Here we are using Field Programmable Gate Array (FPGA) in order to reduce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy efficient Vedic multiplier.There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7o C, 53.5o C, 40o C and 21o C respectively.
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