Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA

Bishwajeet Pandey; Md  Atiqur Rahman; Dil M  Akbar Hussain; Abhay Saxena  and Bhagwan Das

doi:10.17485/ijst/2016/v9i25/96633

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Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2016/v9i25/96633

Year: 2016, Volume: 9, Issue: 25, Pages: 1-12

Original Article

Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA

Bishwajeet Pandey¹ , Md. Atiqur Rahman¹ , Dil M. Akbar Hussain² , Abhay Saxena³ and Bhagwan Das⁴

¹ Gyancity Research Lab, India; [email protected]
[email protected]
² Aalborg University, [email protected]
³Dev Sanskriti Vishwavidyalaya, [email protected]
⁴UTHM, [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

The 8-bit design is able to process 256 times input combination in compare to 4-bit vedic multiplier, using approximates 6 times basic elements, 2 times IO buffers, approximate 1.5 times total power dissipation. HSTL_I_12, SSTL18_I and LVCMOS12 are the most energy efficient IO standards in HSTL, SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA but there is no switching activity. Design static power dissipation of 8-bit Vedic multiplier is almost double of design static power dissipation of 4-bit Vedic multiplier. Device static (leakage) power dissipation of 8-bit Vedic multiplier is almost equal to device static power dissipation of 4-bit Vedic multiplier on 40nm FPGA.
Keywords: HSTL, IO Standards, LVCMOS, SSTL, Static Power Reduction, Vedic Multiplier, Voltage Scaling