Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i4/83322
Year: 2016, Volume: 9, Issue: 4, Pages: 1-5
Original Article
V. Sarada1* and T. Vigneswaran2
1Department of ECE, SRM University, Chennai - 603203, Tamil Nadu, India; [email protected] 2School of Electronics Engineering, VIT University, Chennai - 632014, Tamil Nadu, India; [email protected]
*Author For Correspondence
V. Sarada
Department of ECE, SRM University, Chennai - 603203, Tamil Nadu, India; [email protected]
Objectives: This paper proposes a design of Low power FFT (Fast Fourier Transform) processor used in OFDM (Orthogonal Frequency Division Multiplexing) application as there is demand for low power design of portable communication device. Methods: This FFT processor is based on SDF (Single Path Delay Feedback) pipelined Architecture. Digit slicing multiplier less architecture aids in realizing the complex Multiplication. To reduce power dynamic power dissipation, the proposed architecture applies clock gating buffer. Control circuit is implemented using Gray code sequence instead of binary code sequence. The design proposed here is implemented in Verilog HDL. Cadence tool is used for synthesizing the proposed design Findings: The number of complex multiplication is also reduced by using radix -25 algorithms. The result shows reduced power consumption up to 25%. Improvements: This paper is presented for 64 Point FFT design; this can also be extended for Higher N point FFT design.
Keywords: Clock Gating, FFT, Multiplier Less Multiplier, Radix 25 , SDF
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