Indian Journal of Science and Technology

Abstract

Objectives: Low power consumption, high-speed and low-cost are the major important needs in several applications like Asynchronous Transfer Mode (ATM) and Giga-bit Ethernet networks. To achieve high-speed parallel data comparisons in internet routers PB-CAM is the one of best hardware approaches. In the present work, PB-CAM is modified for improving performance of CAM architecture. Methods/Statistical Analysis: In PB-CAM unit the main building blocks of the process is parameter extractor, parameter comparison circuit and CAM cell. The PB-CAM is faster and low-power consumption than the traditional CAM. The PB-CAM unit implemented by 180nm, 90nm and 45nm CMOS technology in Cadence. The parameterextractor and static-parameter-comparison circuits implemented in 180nm, 90nm and 45nm CMOS technology. Findings: The power consumption of the proposed Parameter-Comparison circuit using XNOR-NAND CMOS logic is 0.02135uW at a supply voltage of 0.45V in 45nm CMOS technology for a 4x4 (4-bits of stored parameter-extracted data and 4-bits of input parameter-extracted data) size parameter comparison data at 10-30MHz. For 15-bit input data, the PB-CAM with proposed parameter comparison circuit is consuming an average power of 129.1uW at a supply of 0.9V and a frequency of 10-30MHz. The results show that the PB-CAM unit using proposed parameter comparison circuit is faster, low-power consumption and low-cost than the PB-CAM with static parameter comparison circuit. Application/Improvements: PBCAM circuit used in high-speed look-up-tables (LUTs), ATMs, routers and etc. In future, further advancements can be done in PB-CAM unit by combining different techniques such as match-line-sense-amplifier, ones-count, block-XOR, parity-bit to achieve low-power, low-cost and high-speed search and read operations in network routers.
Keywords: ATM, Cadence, CAM, Ethernet, High-Speed, Low-Cost, Low Power, Match-Line, PB-CAM, Routers