Low Power Estimation on Test Compression Technique for SoC based Design

P  Raja Gopal   and S  Saravanan

doi:10.17485/ijst/2015/v8i14/61848

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Low Power Estimation on Test Compression Technique for SoC based Design

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2015/v8i14/61848

Year: 2015, Volume: 8, Issue: 14, Pages: 1-5

Original Article

Low Power Estimation on Test Compression Technique for SoC based Design

P. Raja Gopal^1* and S. Saravanan²

¹VLSI Design, SASTRA University, Thanjavur, 613401, India; [email protected]

²School of Computing, SASTRA University, Thanjavur, 613401, India; [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Test power dissipation is one of the major challenging task in System on Chip (SoC). The objective of the paper is to reduce the power consumption during testing in VLSI testing field. This paper analyzes the test power consumption for the test data to get the low power consumption by using switching activity. The Low Power Transition – X filling (LPT-X) method is proposed to reduce the transition switching where unknown bits were filled. Weighted Transition Metric (WTM) method used to estimate low test power. This paper approach achieves reduction of average power consumption by LPT-X filling method. Using ISCAS89 benchmark circuits the experimental results were conducted and achieves 83 percent of reduced average test power.

Keywords: Low Power Transition (LPT), Switching Activity, System on Chip (SoC), Test Power, Weighted Transition Metric (WTM), X-Filling