Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 5, Pages: 1-5
Kishore Sanapala* and R. Sakthivel
*Author For Correspondence
Kishore Sanapala VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India; [email protected]
Background/Objectives: As technology scaling down, subthreshold operation is playing a vital role in the design of digital circuits to achieve ultra low power consumption with considerable performance. Methods/Statistical Analysis: This paper presents a novel body bias technique, where the body terminal of NMOS is reverse biased to VDD which reduces the subthreshold leakage. The basic logic gates are designed using proposed body bias scheme. To analyze the performance, standard 28 transistor full adder cell is implemented using the proposed technique and the performance parameters - power, delay, PDP are calculated and compared with the conventional CMOS Full adder. The simulations are done in cadence 90 nm technology for VDD = 0.2v. Findings: The simulation results show that the circuits designed using the proposed technique achieves more than 31% savings in power and more than 15% savings in PDP than traditional body bias technique used in static CMOS configuration. Applications/Improvements: These circuits are widely applicable in portable battery operated devices such as cellular phones, wearable electronics and remote sensors where ultra low power consumption is required with low to medium performance.
Keywords: Body Bias, CMOS, Full Adder, Logic Gates, Subthreshold Operation, Ultra Low Power
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