• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2023, Volume: 16, Issue: 42, Pages: 3727-3734

Original Article

Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier

Received Date:29 March 2023, Accepted Date:29 September 2023, Published Date:12 November 2023


Objectives: Speed of multiplication in Digital Signal Processing (DSP) applications plays an important role in generating the result quickly. There is scope for reducing the propagation delay in multiplication by designing the multiplier circuit based on the Vedic mathematics (formulas) sutras. This study aims to design the multiplier circuit based on Nikhilam Navatshcaramam Dashath (NND) of Vedic mathematics for improvement in speed, power, and area. Methods: The multiplier circuit based on NND method is designed for the multiplier and multiplicand less than as well as greater than the nearest base in the binary number system. The architecture is designed for both. The proposed multiplier is implemented with VHDL on Vertex-7, Device: XC7VX485T Package: FFG1157, FPGA board using Xilinx ISE 14.7, and its power dissipation is calculated using XPower analyzer. The performance of the proposed multiplier is compared with the conventional array multiplier, Vedic multiplier and also compared with the architecture reported in the literature. Findings: In the proposed architecture n bit multiplier and multiplicand are divided into n/2 bits, two parts, and processed through n/2 bit multiplier and n bit adder. This method converted the n bit multiplication into n/2 bit multiplication and n bit addition. The proposed architecture is efficient in terms of area, delay and power as compared to the array and Vedic Urdhva Tiryakbyham (UT) multiplier. The 4 bit NND multiplier is 26.72 % delay and 47.05 % area efficient as compared to the reported architecture 1. To compare with other reported architecture, the results are also taken on Artix-7, Device: XC7A100T Package: CSG324, and Spartan-6, Device: XC6SLX4 Package: TQG144 FPGA. The results demonstrate an improvement in processing speed as well as power consumption. This method is a special case of multiplication and is efficient if the multiplicand and multiplier are close to the base value. In this implementation, the multiplier and multiplicand are split into two parts and processed; hence, the algorithm will give the correct result for a specific range of multipliers and multiplicands. The accuracy analysis of the proposed multiplier is also performed for multipliers and multiplicands far away from the base value. The maximum error is 7.94%. Novelty: The architecture used in this system converts n-bit multiplication into n bit addition and n/2 bit multiplication, which can be used for the numbers below the base value. For values greater than the base value, on which very little work has been documented in the literature, the NND multiplier is implemented in this study.

Keywords: Array Multiplier, Vedic Multiplier, Urdhva Tiryakbyham(UT) Multiplier, Nikhilam Navatshcaramam Dashath (NND), Filed Programmable Gate Array (FPGA)


  1. Chowdary KKS, Mourya K, Teja SR, Babu GS, Priya SSS. Design of Efficient 16-bit Vedic Multiplier. In: 2021 3rd International Conference on Signal Processing and Communication (ICPSC). (pp. 214-218) IEEE. 2021.
  2. Samyuktha S, Chaitanya DL. VLSI design of efficient FIR filters using Vedic Mathematics and Ripple Carry Adder. Materials Today: Proceedings. 2020;33:4828–4832. Available from: https://doi.org/10.1016/j.matpr.2020.08.391
  3. Kumari S, Sharma K. Implementation of Nobel Vedic Multiplier Using Arithmetic Adder. In: J, IJ, KS, S, B, R., eds. Data Intelligence and Cognitive Informatics. (pp. 209-216) Springer Nature Singapore. 2022.
  4. Kumar U, Sindhuri NB, Subbalakshmi K, Kiranmayi U, P. Performance Evaluation of Vedic Multiplier Using Multiplexer-Based Adders. Lecture Notes in Electrical Engineering. 2019;521. Available from: https://doi.org/10.1007/978-981-13-1906-8_36
  5. Pasuluri BS, Sonti VJKK. Performance Analysis of 8-Bit Vedic Multipliers Using HDL Programming. In: K, A, P, M, G, V., eds. Lecture Notes in Electrical Engineering. (Vol. 601, pp. 1036-1046) Springer Singapore. 2020.
  6. Sona M, Somasundaram V. Vedic Multiplier Implementation in VLSI. Materials Today: Proceedings. 2020;24. Available from: https://doi.org/10.1016/j.matpr.2020.03.748
  7. Kumar BY, Kharwar S, Singh S, Mohammed MKA, Dauwed M. Design and FPGA Implementation of Matrix Multiplier Using DEMUX-RCA-Based Vedic Multiplier. In: Lecture Notes in Networks and Systems. (Vol. 573, pp. 216-224) Springer International Publishing. 2023.
  8. Rani D, Govindarajulu. Implementation of Modified Vedic Multiplier using On Quaternary Signed Digit Number System. Journal of Engineering Sciences. 13(12):111–122. Available from: https://www.jespublication.com/upload/2022-V13I12013.pdf
  9. Deepa A, Marimuthu CN, Murugesan C. An efficient high speed squaring and multiplier architecture using yavadunam sutra and bit reduction technique. Journal of Physics: Conference Series. 2020;1432(1):012080. Available from: https://doi.org/10.1088/1742-6596/1432/1/012080


© 2023 Sayyad & Agarkar. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. Published By Indian Society for Education and Environment (iSee)


Subscribe now for latest articles and news.