• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2018, Volume: 11, Issue: 18, Pages: 1-7

Original Article

Optimization of Power and Area in Multipliers for Image Processing Applications


Objectives: This paper is aimed to find a multiplier to provide a physically compact high speed and low power consumption unit. Being a core part of arithmetic processing unit multipliers are in extremely high demand on its speed and low power consumption. Multiplier plays an important role in today’s digital image processing and various other applications. Methods/Statistical Analysis: In modern embedded electronics devices, power consumption is a first-class design concern. Hardware-level approximation mainly targets arithmetic units, such as adders and multipliers, widely used in portable devices to implement multimedia algorithms, e.g., image and video processing. Findings: Compressor has 5 inputs A, B, C, D and Cin to create 3 outputs Sum, Carry and Cout. The 4 inputs A, B, C and D and the output Sum has identical weight. The input Cin is output from a preceding lower widespread compressor and the Cout output is for the compressor inside the next significant level. Application/Improvements: The approximation multiplier is used to improve the speed and efficiency. It is used to reduce the area and time consumption. It is widely used in the digital image processing, FIR filters, reduce the multiplication procedure. 

Keywords: Approximation Multiplier, Adder, Model Sim, Shifter, Multiplexer


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