Performance Analysis of Single-Wall Carbon Nanotubes and Copper as VLSI Interconnect

Gurleen Dhillon and Neha Raghu

doi:10.17485/ijst/2016/v9iS1/106892

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Performance Analysis of Single-Wall Carbon Nanotubes and Copper as VLSI Interconnect

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2016/v9iS1/106892

Year: 2016, Volume: 9, Issue: Special Issue 1, Pages: 1-6

Original Article

Performance Analysis of Single-Wall Carbon Nanotubes and Copper as VLSI Interconnect

Gurleen Dhillon and Neha Raghu^*

School of Electrical and Electronics Engineering, Lovely Professional University Phagwara - 144411, Punjab, India; [email protected]
[email protected]
*Author for correspondence
Neha Raghu
School of Electrical and Electronics Engineering
Email:[email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

The work in this paper analyses the performance of Single Wall Carbon Nanotube (SWCNT) bundles as VLSI interconnect. Using equivalent RLC circuit models described in this paper, comprehensive analysis of delay and power is done at 22nm technology node for both SWCNT bundle and copper. Results show that SWCNT bundle has smaller value of resistance due to longer mean free path and lesser delay than copper. Therefore, SWCNT bundle is a promising alternative to copper as VLSI interconnect for advanced technology nodes.
Keywords: Carbon Nanotubes, Electromigration, Grain Boundary Scattering, Nanotechnology