Indian Journal of Science and Technology
DOI: 10.17485/ijst/2015/v8i33/71204
Year: 2015, Volume: 8, Issue: 33, Pages: 1-7
Original Article
Sharmila Hemanandh1 * and A. Sivasubramanian2
1 Department of Electronics and Communication Engineering, Sathyabama University, Chennai – 600119, Tamil Nadu, India; [email protected]
2 School of Electronics, Vellore Institute of Technology, Chennai - 600127, Tamil Nadu, India; [email protected]
Multipliers are the basic building blocks of signal processing and arithmetic based systems. The objective of this paper is to design a high speed multiplier that significantly improves the performance of many high performance DSP, multimedia and communications systems. This paper proposes a high speed radix 8 Booth multiplier employing signed digit representation for recoding and radix 8 modified Booth algorithm that reduces the number of partial products to n/3. The design of the multiplier is based on Wallace tree architecture with considerable improvement in performance. This paper compares the performance of conventional multiplier with radix 4 tree based Booth multiplier and radix 8 tree based Booth multiplier. The radix 8 tree based Booth multiplier is synthesized using Quartus II simulation tool. The proposed radix 8 tree based multiplier exhibits better performance with respect to area and operating frequency when compared to conventional multiplier.
KeyWords: Higher Radix Booth Multiplier, Partial Product Reduction, Wallace Tree Multiplier
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