Indian Journal of Science and Technology
Year: 2015, Volume: 8, Issue: 24, Pages: 1-7
R. Praveena1* and S. Nirmala2
1 Department of Electronics and Communication Engineering, Sengunthar College of Engineering, Tiruchengode - 637 205, Namakkal, Tamil Nadu, India; [email protected]
2 Department of Electronics and Communication Engineering, Muthayammal Engineering College, Rasipuram - 637408, Namakkal, Tamil Nadu, India; [email protected]
This paper introduces a framework for the implementation of high throughput Multiplier for low Power Biomedical Signal Processing System-on-Chip (SoC) design for Portable ECG Monitoring Systems. In this paper the realization of Efficient Multiplier for the proposed architecture in the implementation of the Biomedical Signal SoC monitoring system is presented. Since the multiplier is the part of the processor core which needs more attention and a modified approach of generating partial product for successful multiplication of the bit streams has been presented. The proposed SoC incorporates a new architecture using the booth multiplier and sign extension multiplier for 4 bit, 8 bit and 16 bit performing multiplication on both signed and unsigned number. The implementation is further extended on the radix application of booth multiplier and sign extension method. Different parameters have been compared for both signed and unsigned multiplier. The implementation is done through VHDL on Quartus II synthesizer for Cyclone II family.
Keywords: Bit Serial Multiplier, MAC Unit, Radix Algorithm and Booth Recoding, Sign Extension, System on Chip
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