Indian Journal of Science and Technology
Year: 2017, Volume: 10, Issue: 16, Pages: 1-6
Preethi M. Nair, Rajesh Mehra and Chandni
Objectives: This paper highlights the design of multiplier-less FIR filter. The binary coefficients are replaced by Canonic Signed Digit representation which reduces the complexity of the design. Methods/Statistical Analysis: In the current scenario more research is going on the optimization of Finite Impulse Response filters with less complex hardware design. The FIR filters performance depends on number of coefficient multipliers. The multipliers are expensive in terms delay area and power. In the CSD based filter, the number of non-zero bits is reduced. This proposed filter is designed in MATLAB, simulated in ISE environment and implemented on FPGA. Findings: The proposed filter is implemented on three FPGA devices, Xilinx’s Spartan-3E, xc3s500e-4fg320, Virtex 2P, 2vp30ff1152-5 and Virtex 5P xc5v1x50t-3ff1136. Improvements: The designed structure uses reduced number of hardware components like slices, look up tables (LUTs) and flip-flops as compared to different structures and offers better performance.
Keywords: CSD, DSP, FIR, FPGA, IIR
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