Indian Journal of Science and Technology

Abstract

Background/Objectives: The Complementary Metal–Oxide–Semiconductor (CMOS) scaling feature was the wonderful feature which led the electronics market into in an era of miniaturization but with the fascinating feature some limitations has also been observed. Methods/Statistical analysis: CMOS technology has also given a new horizon to the memory circuits like Static Random-Access Memory (SRAMs). To overcome the limitations of scaling of the CMOS technology, Fin Field Effect Transistor (FinFET) technology has been chosen. To overcome the limitations of scaling of the CMOS technology, FinFET technology has been chosen. Like CMOS SRAMs, FinFET SRAMs have also gained popularity because of the advantages as discussed in this paper. Findings: In this paper, FinFET SRAM cells have been proposed in three different configurations for better stability and reduced leakage power in sub threshold region at 20nm technology.4 different modes of FinFET has been used to implement the SRAM. The FinFETs are classified as (i) SG-mode (ii) LP-mode and (iii) IG mode. A comprehensive analysis has been made for all the 4 types of SRAM stability which includes for Read Margin, Write Margin, Hold Margin and leakage power analysis by finding the leakage current for all the proposed circuits and has compared with the previous work and it has been found that the proposed circuits serves better in terms of stability and reduced leakage current. The cell has been implemented for sub threshold voltages ranging from 0.4V to 0.1V. The maximum Write Margin at 0.4V is 196.9mV, Read Margin is 110 mV. Application/Improvements: It has been found that from the different SRAM circuits, IG-P has the maximum Write SNM, Read SNM and hold margin while LP mode has minimum leakage current, next the IG-P mode FinFET.

Keywords: FinFET, Leakage Current, Read Margin, SRAM, Write Margin