Indian Journal of Science and Technology

Abstract

Background: Fast Fourier Transform (FFT) operation is one of the most important fundamental operations in the digital signal processing systems. In this paper, a new pipelined Radix-8 based Fast Fourier Transformation (FFT) architecture is designed for performing frequency transformation techniques. The objective of this paper is to improve the speed and to reduce the area, delay and power. Methods: Radix-8 FFT, which is used to improve the speed of functioning by reducing the computational path. In the proposed new architecture named as “Radix-8 combined SDF-SDC FFT”. In this architecture, the numbers of stages are reduced to 75%. The first two stages are designed using Single path delay feedback and the last two stages are designed using single-path-delay Commutator. The combined SDF-SDC FFT is to increasing the processing speed of architecture. In the proposed “pipelined Radix-8 combined SDF-SDC FFT’’ is designed in this article. Findings: In the existing Radix-8 SDF FFT, the number of stages is increased. In order to reduce the number of stages, Radix-8 combined SDF-SDC FFT has been proposed. The performance evaluation of Radix-8 combined SDF-SDC FFT architecture is determined through Very Large Scale Integration (VLSI) system design environment. In the VLSI system design, less area utilization, low power consumption and high speed are the main parameters. Hence, the main goal of proposed architecture is to reduce hardware complexity, power consumption and increasing both speed and throughput of the system. Applications: Mobile Ad-hoc Network (MANET), Orthogonal Frequency Division Multiplexing (OFDM) System, Telecommunication networking system are considered as the important applications of proposed radix-8 combined SDF-SDC FFT.
Keywords: Fast Fourier Transform (FFT), Single-path Delay Commutator (SDC) FFT, Single-path Delay Feedback (SDF) FFT, Very Large Scale Integration (VLSI)