VLSI Implementation of Area-Efficient and Low Power OFDM Transmitter and Receiver

D  Kalaivani   and S  Karthikeyen

doi:10.17485/ijst/2015/v8i18/63062

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VLSI Implementation of Area-Efficient and Low Power OFDM Transmitter and Receiver

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2015/v8i18/63062

Year: 2015, Volume: 8, Issue: 18, Pages: 1-6

Original Article

VLSI Implementation of Area-Efficient and Low Power OFDM Transmitter and Receiver

D. Kalaivani ^* and S. Karthikeyen

VLSI Design, Sathyabama University, Chennai - 600119, Tamil Nadu, India; [email protected], [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Background: This paper consists of an analysis of Fast Fourier Transform (FFT) architectures which are the backbone of any OFDM based wireless networks. Methods: By using the FFT concepts we are indeed in developing an efficient architectures for wireless networks which are common in everywhere now-a-days, Our concepts are purely based upon in development we have to test it by using Field Programmable Gate Array (FPGA),we are using Xilinx based Spartan-3e FPGA. Results: The concepts are simulated by using Modelsim6.3c and to synthesize by using Xilinx ISE 10.1.
Keywords: FFT, FPGA, OFDM, SDF-SDC