Indian Journal of Science and Technology
DOI: 10.17485/ijst/2015/v8i35/81204
Year: 2015, Volume: 8, Issue: 35, Pages: 1-6
Original Article
P. Sivaranjani1* and A. Senthilkumar2
1 Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai – 638052, Tamil Nadu, India; [email protected]
2 Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi - 642003, Tamil Nadu, India; [email protected]
Background: Floorplanning is important step in physical design automation of VLSI circuits, because it gives an early feedback on the architectural design. It is the process of finding the position of the module such that no two modules overlap with each other. Methods: In order to have an efficient floorplan, the total area occupied by the modules should be minimum. So, non-slicing floorplan is used to find an optimal floorplan layout. To represent non-slicing floorplan, a number of representations are proposed. Findings: To encompass billions of transistors in an Integrated Circuit (IC), 3Dimensional (3D) IC is preferred instead of 2D. In this paper, a novel 3Dimensional (3D) non-slicing floorplanning representation called Modified Corner List (MCL) algorithm is proposed and properties of MCL algorithm is derived. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits and simulation results shows that it is very effective for 3D floorplan representation. Improvements: The proposed algorithm works well for small number of modules. As the number of module increases, computational time taken by the algorithm also increases. The above problem can be solved by applying heuristic algorithm in association with MCL strategy to find near optimal placement in reduced run time.
Keywords: MCNC Benchmark Circuits, Modified Corner List, 3D Non-Slicing Floorplan, VLSI
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