• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 16, Pages: 1-4

Original Article

A Systematic Approach to CMOS Low Noise Amplifier Design for Low Power Transmission


Recent interest in 60 GHz band for high-density and short range wireless links has led to significant progress in milli-metre (mm) wave radio systems. The Low Noise Amplifier (LNA) serves as the first component in the Radio Frequency (RF) transceiver system. The performance of LNA determines the sensitivity and selectivity of the system. In order to maximize performance gain, Noise Figure (NF) and input matching of LNA need to be optimized. A LNA for 60 GHz is designed. The main topology used in our design is cascode with a middle inductor and a Common Source (CS) configuration. The design is laid out on 130 nm CMOS standard technology. LNA is designed using classical noise matching techniques. Simulated results shows a very low noise figure of 1.3 dB with a gain of 9.8 dB and the reflection coefficientis-11.5 dB. The proposed LNA can be very well used in biomedical applications in research areas like neurology and other short range applications.

Keywords: CMOS, Cascode Topology, CS Configuration, 60 GHz, LNA 


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