• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 17, Pages: 1-5

Original Article

An Effective on-Chip Network Topology for Network on Chip (Noc) Trade-Offs


Background/objectives: The major contribution in very large scale integrated circuits is given by System on Chip (SoC) technology. Many fuzzy logics are been implemented on SoC’s and are effectively supported by them. In time the Networks came into existence and interconnection of networks became very necessary so Network on Chips (NoC) was implemented and many topologies were also suggested. The main aim of this paper is to find an effective on-chip topology for network on chips. Methods/Statistical Analysis: Topologies related to this network on chips gives different routing algorithms which defines the direction of the route. Different algorithms were proposed for different topologies defining the direction, traffic rate at which the packet is entering, latency, and throughput. These were considered as the main trade off’s for Network on Chip. Findings: in this paper discussion on 4 topologies was done by taking few main properties into account and implementation of the topologies were done in software. It was found that latency and throughput plays a major role in the topology and along with these 2 the packet rate and flit rate also play a key role. The values of all trade-offs for every topology were taken and graphs were plotted showing the variation between the topologies. The efficiency of each topology can be observed in respective graph. Application/Improvements: Network on chips is used in routers and these can be further improved in to wireless connections.

Keywords: Interconnection Networks, Latency, Routing algorithm Throughput, Topology 



Subscribe now for latest articles and news.