• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 5, Pages: 1-7

Original Article

An Efficient Single Precision Floating Point Multiplier Architecture based on Classical Recoding Algorithm


Background: Floating Point (FP) multiplication has found its importance in many microprocessors but it is very difficult to implement on FPGA because of its complicated internal computation. Methods: We investigate partial product (PP) reduced FP multiplication based on Radix-4 Booth Encoded Algorithm (BEA). Radix-4 BEA reduces the number of PP generation by half. PP reduction performed in three steps such as Grouping bits (3-bit for each group), Encode the group and PP calculation for each group. Findings: The investigation results show that Radix-4 BEA works perfectly on signed multiplication and unsigned (FP mantissa) multiplication needs some extra consideration. Radix-4 BEA grouping multiplier bits need overlapping one bit from both adjacent group that limits block and parallel processing. 2’s complement calculation and sign extension essential for PP generation that increases the resource utilization. In this paper, 32 bit improved FP multiplication based on classical recoding and parallel processing method is proposed. Classical recoding reduces PP generation by half without overlapping, sign extension and 2’s complement. 24 bit mantissa split into blocks (8 bit each) and each block is recoded using classical recoding algorithm and all blocks are performed in parallel. Applications: The experimental results show that our proposed design runs with high frequency with less resource utilization and suitable for signal processing applications. 

Keywords: Block Multiplication, Classical Recoding, Floating Point Multiplier, Parallel Processing, Single-Precision


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