Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 8, Pages: 1-5
S. Ranjith1 * and T. Vishnupriya2
1Department of ECE, Jeppiaar Engineering College, Chennai- 600119, Tamil Nadu, India; [email protected] 2VLSI Design, Jeppiaar Engineering College, Chennai-119, Tamil Nadu, India; [email protected]
*Author for Correspondence
S. Ranjith Department of ECE, Jeppiaar Engineering College, Chennai- 600119, Tamil Nadu, India; [email protected]
Background/Objectives: Fast Fourier transforms (FFT) has become ubiquitous in many engineering applications. FFT is one of the most employed blocks in many communications and signal processing systems. This paper aims in designing SDF architecture for efficient FFT algorithms.Methods/Statistical analysis: Efficient algorithms are being designed to improve the architecture of FFT.Higher Radix FFT algorithms have the traditional advantage of using less numbers of computational elements and are more suitable for calculating FFT of long data sequence.Findings:In designing SDF architecture for efficient FFT algorithms like Radix 2, Radix 4 and Radix 22 ,thedesigns are compared by performing simulations using VERILOG HDL and power analysis. The comparison includes the number of logic gates used by every architectures and their power dissipation using various devices. Trade-off between accuracy, speed, hardware complexity and power consumption should be made so as to choose the best fit architectures for the given application.Improvements/Applications:From the comparison results, best fit architecture is chosen and is implemented at the software level for the desired device for the Multiple Input Multiple Output (MIMO) application using Orthogonal Frequency Division Multiplexing (OFDM) employed in 4G technologies.
Keywords: Fast Fourier Transform (FFT), Multiple Input Multiple Output (MIMO), Pipelined FFT, Power Analysis
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