Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i2/86343
Year: 2016, Volume: 9, Issue: 2, Pages: 1-6
Original Article
J. Thameema Begum1* , S. Harshavardhan Naidu2 , N. Vaishnavi1 , G. Sakana1 and N. Prabhakaran1
1Electronics and Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Avadi, Chennai – 600062, Tamil Nadu, India; [email protected], [email protected], [email protected], [email protected] 2Electronics and Electrical Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Avadi, Chennai – 600062, Tamil Nadu, India; [email protected]
*Author For Correspondence
J. Thameema Begum
Electronics and Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Avadi, Chennai – 600062, Tamil Nadu, India; [email protected]
Background/Objectives: The main objective of the paper is to implement a reconfigurable ALU that is a combination of a 32-bit floating point adder/subtractor and integer ALU. The integer ALU performs integer functions and logical operations such as addition, subtraction, shifting and comparison. Methods/Statistical analysis: In this paper, a 32-bit single precision format based on IEEE754 standard for the floating-point unit, with a 23-bit mantissa, 8-bit exponent and 1-bit sign value is considered. Findings: Verilog Hardware Description Language (HDL) is used and simulated by model sim simulator and then synthesized with Spartan3E FPGA. The functional unit uses 25% number of slices, 9% number of slice flip-flops, 18% of 4 input LUTs. From the timing report, the maximum frequency obtained is 81.614MHz. The maximum power obtained by the system is 82.46mW. Applications/Improvements: This can be used for data-parallel and computation intensive applications and in multimedia applications.
Keywords: Field Programmable Gate Arrays (FPGA), Hardware Description Language (HDL), Reconfigurable Arithmetic Logic Unit
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