Indian Journal of Science and Technology
Year: 2017, Volume: 10, Issue: 38, Pages: 1-5
Y. L. Ajay Kumar1 , D. Satyanarayana2 and D. Vishnu Vardhan1
1Department oF E.C.E, Jawaharlal Nehru Technological University Anantapur, Anantapur – 515002, Andhra Pradesh, India; [email protected], [email protected] 2Department of E.C.E, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyala – 518501, Andhra Pradesh, India; [email protected]
Network-On-Chip (NOC) plays an important role in improving the performance of multi-core systems. Objectives: This paper proposes an alternative architecture for Networking-On-Chip which will improvise the Routing Efficiency of Network-On-Chip. Methods/Statistical Analysis: In the presented alternative architecture, we used a routing technique which uses Agents which are designed and made as a part of routing logic. We designed Hand-shake and multi-point packet injection systems. Findings: We introduced a Global routing mechanism and Temperature parameters in the design. This design is scalable to Hetero-generous and Homogeneous networks, it is power efficient. The experimental results reduces the Area, Power and Latency, And increases the Efficiency of the system. Application/Improvements: Routing efficiency for Heterogeneous MpSOC.
Keywords: Agents, Global Routing, Network On Chip (NOC), Processing Elements, Routing Techniques
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