Extensible On-Chip Interconnect Architecture and Routing Methodology for NOC

Y  L  Ajay Kumar; D  Satyanarayana  and D  Vishnu Vardhan

doi:10.17485/ijst/2017/v10i38/115032

Article

Extensible On-Chip Interconnect Architecture and Routing Methodology for NOC

VIEWS 808
PDF 296

Abstract
Full-Text HTML
Full-Text PDF
How to Cite

Indian Journal of Science and Technology

DOI: 10.17485/ijst/2017/v10i38/115032

Year: 2017, Volume: 10, Issue: 38, Pages: 1-5

Original Article

Extensible On-Chip Interconnect Architecture and Routing Methodology for NOC

Y. L. Ajay Kumar¹, D. Satyanarayana² and D. Vishnu Vardhan¹

¹Department oF E.C.E, Jawaharlal Nehru Technological University Anantapur, Anantapur – 515002, Andhra Pradesh, India; [email protected], [email protected]²Department of E.C.E, Rajeev Gandhi Memorial College of Engineering and Technology, Nandyala – 518501, Andhra Pradesh, India; [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Network-On-Chip (NOC) plays an important role in improving the performance of multi-core systems. Objectives: This paper proposes an alternative architecture for Networking-On-Chip which will improvise the Routing Efficiency of Network-On-Chip. Methods/Statistical Analysis: In the presented alternative architecture, we used a routing technique which uses Agents which are designed and made as a part of routing logic. We designed Hand-shake and multi-point packet injection systems. Findings: We introduced a Global routing mechanism and Temperature parameters in the design. This design is scalable to Hetero-generous and Homogeneous networks, it is power efficient. The experimental results reduces the Area, Power and Latency, And increases the Efficiency of the system. Application/Improvements: Routing efficiency for Heterogeneous MpSOC.

Keywords: Agents, Global Routing, Network On Chip (NOC), Processing Elements, Routing Techniques