Indian Journal of Science and Technology

Abstract

This paper presents a novel architecture design for forward error correction technique based on RS coding scheme for wireless applications. The design was created using System Generator for DSP tool from Xilinx and was simulated on Matlab/Simulink environment. The hardware description language source code for different blocks was generated and the design was subjected to severe functional and timing constraints using Xilinx Foundation series and ModelSim tools. Synplify Pro tool was finally used to synthesize the complete design. The overall architecture for RS Coder-Decoder was implemented on Xilinx Virtex-II XC2v250 device and consumed slices 1429 for the CODEC at a clock frequency of 90 MHz. The architecture design power consumption analysis was done using the Xilinx Xpower tool and it came out to be about 783 mW.
Keywords: FPGA, Reed-Solomon coding