FPGA implementation of improved version of the Vigenere cipher

Massoud Sokouti; Babak Sokouti; Saeid Pashazadeh  and Leili Mohammad Khanli

doi:10.17485/ijst/2010/v3i4.9

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FPGA implementation of improved version of the Vigenere cipher

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2010/v3i4.9

Year: 2010, Volume: 3, Issue: 4, Pages: 459-462

Original Article

FPGA implementation of improved version of the Vigenere cipher

Massoud Sokouti¹ , Babak Sokouti² , Saeid Pashazadeh¹ and Leili Mohammad Khanli^3*

¹ Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran;
² Faculty of Engineering, Islamic Azad University-Tabriz Branch, Tabriz, Iran;
³ Faculty of Mathematical Sciences, University of Tabriz, Tabriz, Iran.
[email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

The use of cryptography has become increasingly important in recent years. Currently there are several good methods for encryption like AES and DES. Both of these algorithms require several rounds to encrypt a relatively small block of data. Stream ciphers, like Vigenere and Caesar in particular, only require one round. The Vigenere and Caesar ciphers, however, can be easily broken. Improved version of the Vigenere algorithm is obtained by adding random bits of padding to each byte to diffuse the language characteristics and this make the cipher unbreakable. In this paper we will present an efficient method for hardware implementation of the improved Vigenere algorithm.
Keywords: Cryptography; Vigenere algorithm; FPGA.