Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i44/101948
Year: 2016, Volume: 9, Issue: 44, Pages: 1-7
Original Article
P. Nithin* , N. Udaya Kumar2 and K. Bala Sindhuri3
SRKR Engineering College, Bhimavaram - 534204, Andhra Pradesh, India; nit[email protected], [email protected], [email protected]
*Author for correspondence
P. Nithin
SRKR Engineering College, Bhimavaram - 534204, Andhra Pradesh, India; [email protected]
The circuit used to add the two numbers or two bits is adder. The main problem with the adder is both the area and delay to produce the final output. So, this paper implements an adder it requires a less amount of delay and area to produce the final output. The reduction of delay and area is done by the Parallel Prefix Adders. It plays a prominent role in Digital Combinational Circuits. Area and power are other factors which really makes the adder effective. The techniques used to get a less amount of delay and area is by using the Binary-to-Excess-1 Converter (BEC) and a Parallel Prefix Adder. The delay of the Modified Linear Carry Select Adder of Brent Kung Adder is less when compared with the Regular Carry Select Adder architecture. The delay and area further can be improved by using a Square root Carry Select adder. This paper focuses on operation of Parallel Prefix Adders of 32 bit Brent-Kung Adder.
Keywords: And-Or-Inverter (AOI) Logic, Binary-to-Excess-1 Converter (BEC), Brent-Kung (BK) Adders, Carry Select Adder (CSLA), Parallel Prefix Adder
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