Indian Journal of Science and Technology
DOI: 10.17485/ijst/2014/v7i3.13
Year: 2014, Volume: 7, Issue: 3, Pages: 276-281
Original Article
Amin Malekpour and Alireza Ejlali*
Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
*Author for the correspondence:
Alireza Ejlali
Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
E-mail: [email protected]
Received Date:01 February 2014, Accepted Date:22 February 2014, Published Date:03 March 2014
Decimal arithmetic has gained intensive attention in the last decade. Most commercial, financial, scientific, and internet-based applications need their data to be precise, while binary number system loses preciseness in some cases. The latency and area are two major factors in existing research works on decimal multiplication. However, energy/power consumption is another important factor in today’s digital systems. Hence, in this paper we proposed a new low power decimal adder based on prediction technique for decreasing the energy/power consumption of parallel decimal multiplication and show its impacts on one of the well-known parallel decimal multipliers architecture. Our observations show 11.5% improvement in terms of total power consumption and 10.13% improvement in terms of energy consumption.
Keywords: Decimal Adder, Decimal Multiplication, Energy Consumption, Parallel Multiplier, Power Consumption
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