Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 45, Pages: 1-6
Kanan Bala Ray1 , Sushanta K. Mandal2 and B. Shivalal Patro1*
*Author for correspondence
B. Shivalal Patro KIIT University, Bhubaneswar - 751024, Odisha, India; [email protected]
Objective: Leakage power is the major concern of circuit designers in nano meter technology era. The objective of this work is to design a low leakage power floating gate MOS static random access memory. Methods/Statistical Analysis: The proposed design has been made using Floating Gate MOS (FGMOS) and Leakage Control Transistor (LECTOR) technique. FGMOS has been used in place of normal MOS on the conventional SRAM cell. In the LECTOR an NMOS transistor is incorporated between output and pull down the network and a PMOS transitor is incorporated between output and pull up a network. Findings: The SRAM cell has been designed and simulated in Cadence environment on 45 nm gpdk standard CMOS process technology. From the simulation results, it is found that LECTOR FGSRAM cell reduces 90.53% leakage power, 12% delay and 33.20% overall power consumption when compared to FGSRAM cell. A detailed comparison between FGSRAM cell and LECTOR FGSRAM cell performances has been reported during WRITE operation mode. Application/ Improvements: It is found that hybrid technique should be added along with LECTOR to improve the parameters.
Keywords: Floating Gate SRAM, High Speed, Hybrid Techniques, LECTOR, Low Leakage Power
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