• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2021, Volume: 14, Issue: 20, Pages: 1699-1710

Original Article

Low Power PPN inverter based 10T SRAM Cell

Received Date:07 March 2021, Accepted Date:16 May 2021, Published Date:11 June 2021


Objectives: In the present power-hungry world, the objective of this paper is to design a system that helps in the reduction of power consumption of systems. A memory cell, more specifically an SRAM cell being the major contributor to the increased power becomes an important unit to be considered in such systems for reducing power. This paper presents an improved single-ended PPN inverter based 10T SRAM cell. Methods: The proposed cell makes use of PPN-inverters. The CMOS inverter is replaced by the PPN-inverter in the conventional 8T SRAM cell giving an improved single-ended PPN-based 10T SRAM cell. Findings: The proposed work is compared with other SRAM cells based on delay, power dissipation, and power delay product (PDP). The proposed cell is designed and simulated on Cadence Virtuoso EDA tool version IC6.1.7 at a standard CMOS 45nm technology. The simulation results show that the proposed SRAM cell consumes lesser power and hence lower PDP compared to conventional 8T SRAM cell as well as other SRAM cells and with the use of high threshold voltage transistors in the read circuit a further decrease in the power consumption is observed. So, by use of PPN inverter in 8T SRAM cell a new design for low power consuming SRAM cell is achieved. Novelty: The proposed cell is optimized in terms of power dissipation making it more efficient for use in portable battery-operated devices.


10T SRAM cell, Low power, PPN inverter, Static Random­Access Memory (SRAM)


  1. Khokhara NK, Nagpapa BH. Comparative Analysis of 1 bit SRAM using Different SRAM cells in 45nm CMOS Technology. International Journal of Innovative Research in Computer and Communication Engineering. 2017;5(1):251–258.
  2. Rehlan S, Yadav A, Goel B, Raheja J. Comparative analysis of low power 4T SRAM cell. International Journal of Technical Research. 2014;3(1):1–4. Available from: http://www.omgroup.edu.in/downloads/files/n532d18cf4378f.pdf
  3. Kumar HV, Shah O. Design and analysis of SRAM cell for ULP application. International Research Journal of Engineering and Technology. 2016;3(4):1930–1942. Available from: https://www.irjet.net/archives/V3/i4/IRJET-V3I4382.pdf
  4. Carlson I, Anderson S, Natarajan S, Density AAH. Low Leakage, 5T SRAM for Embedded Caches. Proceedings of the 30th European Solid-State Circuits Conference. 2004;p. 215–218. Available from: 10.1109/ESSCIR.2004.1356656
  5. Chang L, Fried DM, Hergenrother J, Sleight JW, Dennard RH, Montoye RK, et al. Stable SRAM cell design for the 32nm node and beyond. Proceedings of the IEEE Symposium on VLSI Technology. 2005;p. 128–129. Available from: 10.1109/.2005.1469239
  6. Liu Z, Kursun V. Characterization of a Novel Nine-Transistor SRAM Cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2008;16(4):488–492. Available from: https://dx.doi.org/10.1109/tvlsi.2007.915499
  7. Lo CH, Huang SY. PPN based 10T SRAM cell for low-leakage and resilient subthreshold operation. IEEE J. Solid State Circuits. 2011;46(3):695–704. Available from: 10.1109/JSSC.2010.2102571
  8. Kulkarni JP, Kim K, Roy K. A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM. IEEE Journal of Solid-State Circuits. 2007;42(10):2303–2313. Available from: https://dx.doi.org/10.1109/jssc.2007.897148
  9. Kulkarni JP, Roy K. Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2012;20(2):319–332. Available from: https://dx.doi.org/10.1109/tvlsi.2010.2100834
  10. Ahmad S, Gupta MK, Alam N, Hasan M. Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2016;24(8):2634–2642. Available from: https://dx.doi.org/10.1109/tvlsi.2016.2520490
  11. Sanvale P, Gupta N, Neema V, Shah AP, Vishvakarma SK. An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network. Microelectronics Journal. 2019;92. Available from: https://dx.doi.org/10.1016/j.mejo.2019.104611
  12. Sachdeva A, Tomar VK. Design of 10T SRAM cell with improved read performance and expanded write margin. IET Circuits, Devices & Systems. 2021;15:42–64. Available from: https://dx.doi.org/10.1049/cds2.12006
  13. Sachdeva A, Tomar VK. Design of multi-cell upset immune single-end SRAM for low power applications. AEU - International Journal of Electronics and Communications. 2021;128. Available from: https://dx.doi.org/10.1016/j.aeue.2020.153516
  14. Shah AP, Yadav N, Beohar A, Vishvakarma SK. Process Variation and NBTI Resilient Schmitt Trigger for Stable and Reliable Circuits. IEEE Transactions on Device and Materials Reliability. 2018;18(4):546–554. Available from: https://dx.doi.org/10.1109/tdmr.2018.2866695
  15. Singh A, Jain P, Gupta TK. A Comparative Analysis of Improved 8T SRAM Cell with Different SRAM Cell. Int. Journal of Engineering Research and Applications. 2015;5(4):120–127. Available from: http://www.ijera.com/papers/Vol5_issue4/Part%20-%206/S50406120127.pdf
  16. Rabaey J, Chandrakasan A, Nikolic B. Digital Integrated Circuits: A Design Perspective (2nd). Englewood Cliffs, NJ. Prentice Hall. 2002.
  17. Aparna, RC. A study of Different SRAM Cell Designs. International Journal of Emerging Trends in Engineering Research. 2021;9(3):303–309. Available from: http://www.warse.org/IJETER/static/pdf/file/ijeter24932021.pdf


© 2021 Aparna & Chauhan. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. Published By Indian Society for Education and Environment (iSee)


Subscribe now for latest articles and news.