Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 37, Pages: 1-5
K. Kiron, B. Srinath, Pochamreddy Satishwar Reddy and Husnul Budhiraja
Objectives: Power consumption in digital systems is a crucial issue with the greater emphasis on nano-scaled technologies. Power consumption is greatly curbed by reducing the voltage levels. However, this compromises the circuit delay. Also, by decreasing the voltage level, circuit delay rises exponentially and hence there is an increase in static energy consumption. Methods/Statistical Analysis: In this paper, adders are the architectures chosen for optimization due to the fact that in most of the modern digital systems, the maximum operating speed depends on how fast adders can process the data. This, in turn, is responsible for setting the minimum clock cycle time in processors. The primary focus of this paper is to reduce the delay of Serial Full Adder (SFA), a sequential adder. The delay, power, and area of six different 16-bit adders are examined and compared with respect to their structure and logic depth. This paper presents optimized architectures for 32-bit and 64-bit SFA which operates with less delay and occupies less area by using massively parallel structures. Introducing the concept of neural networks helps us to formulate a power estimation method for adder architectures in SOC Using supervised learning method in Feed Forward Back Propagation Network, the estimated dynamic, leakage and total power is obtained for SFA for any desired input voltage. Findings: The experimental results shows that proposed SFA provides better results with power and delay as metric. The convergence of the proposed estimation method based on neural networks is faster due to its learning and training. Application/Improvements: This method can be extended to estimate the power of any adder architecture and using any other neural network.
Keywords: Adder Architecture, Power Consumption, Neural Networks, VLSI Power Estimation Method.
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