Low power add-one circuit IPGL based high speed square root carry select adder

B S Premananda; Archit Bajpai; G Shakthivel; A R Anurag

doi:10.17485/IJST/v14i9.343

Article

Low power add-one circuit IPGL based high speed square root carry select adder

VIEWS 1472
PDF 853

Indian Journal of Science and Technology

DOI: 10.17485/IJST/v14i9.343

Year: 2021, Volume: 14, Issue: 9, Pages: 776-786

Original Article

Low power add-one circuit IPGL based high speed square root carry select adder

B S Premananda^1*, Archit Bajpai¹, G Shakthivel¹, A R Anurag¹

¹Department of Electronics and Telecommunication, RV College of Engineering, Bengaluru,
560059, India

*Corresponding Author
Email: [email protected]

Received Date:24 February 2021, Accepted Date:09 March 2021, Published Date:19 March 2021

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Background: An adder is the basic building block of any circuitry. Most ripple carry adders suffer from carry rippling which constrains its performance due to increased delay though they occupy less area. Objectives: To design and implement a high speed adder to overcome the carry rippling, which should consume less power and also operate at higher frequency. Method: Squareroot CSLA architecture is designed by replacing ripple carry adder with of Add- One Circuit (AOC) to minimize the area and carry rippling delay. Improved Pass-Gate Adiabatic Logic (IPGL) is incorporated in the proposed SCLSA to reduce power and to increase frequency of operation. Cadence Virtuoso and Spectre is used to design and simulate the adder circuits in CMOS 180nm technology. Findings: We proposed SCSLA adder, which consumed 89% lesser power compared to the reference architecture at 400 MHz operating frequency with a power saving factor of 7.3. Results were verified by simulating up to 1 GHz frequency. Novelty: Incorporation of AOC in the design of square-root CSLA with adiabatic logic (IPGL) incorporated results in lesser power consumption and also adder operates in the higher frequency (GHz).

Keywords: AL; AOC; BEC; IPGL; low power

References

Vishwaja S, Mahendra N. Performance Comparison of Carry Select Adder with Different Techniques. International Journal of Emerging Technology in Computer Science and Electronics. 2016;20(2):25–28. Available from: www.ijetcse.com/ view_paper.php?id=42&iid=42
Ramkumar B, Kittur HM. Low-Power and Area-Efficient Carry Select Adder. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2012;20(2):371–375. Available from: https://dx.doi.org/10.1109/tvlsi.2010.2101621
Abhiram T, Ashwin T, Sivaprasad B, Aakash S, Anita JP. Modified Carry Select Adder for Power and Area Reduction. In: 2017 International Conference on Circuit ,Power and Computing Technologies. (pp. 1-8).
Hasan M, Islam MS, Ahmed MR. Performance Improvement of 4-bit Static CMOS Carry Look-Ahead Adder using Modified Circuits for Carry Propagate and Generate Terms. Systems and Signal Processing. 2019;8(2):76–81. Available from: https://doi.org/10.11648/j.cssp.20190802.16
Teichman P. Introduction in Adiabatic Logic. Springer Series in Advanced Microelectronics. 2012;34.
Yadav R, Bakshi A, Chowdhury J, Das JK. Adiabatic Approach for Charge Restoration in Low Power Digital Circuits. In: International Conference on Inventive Systems and Control. (pp. 473-477) 2018.
Varga L, Kovacs F, Hosszu G. An Improved Pass-gate Adiabatic Logic. In: 14th Annual IEEE International ASIC/SOC Conference. (pp. 208-211).
Priya R, Kumar JS. Enhanced Area Efficient Architecture for 128 bit Modified CSLA. In: 2013 International Conference on Circuits, Power and Computing Technologies. (pp. 989-992).
He Y, Chang CH, Gu J. An area efficient 64-bit Square Root Carry-Select Adder for Low Power Applications. In: IEEE International Symposium on Circuits and Systems. (Vol. 4, pp. 4082-4085) 2005.
Ganavi MG, Premananda BS. Design of Low-Power Square Root Carry Select Adder and Wallace Tree Multiplier using Adiabatic Logic. In: International Conference on Emerging Research in Electronics, Computer Science and Technology. (Vol. 545, pp. 767-781) Springer. 2020.
Bajpai A, Anurag AR, Shakthivel G, Premananda BS. Design of Low Power and High-Speed 16-bit Square Root Carry Select Adder using AL. In: 3rd International Conference on Circuits, Control, Communication and Computing. (pp. 1-4) 2018.
Sasipriya P, Bhaaskaran VSK. Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL) Journal of Circuits, Systems and Computers. 2018;27(04). Available from: https://dx.doi.org/10.1142/s0218126618500524
Premananda BS, Ganavi MG. Performance Analysis of Low Power 8-Tap FIR Filter using PFAL. International Journal of Innovative Technology and Exploring Engineering. 2019;8(8):365–374. Available from: www.ijitee.org/wp-content/uploads/papers/v8i8/ H6357068819.pdf
Ganavi MG, Premananda BS. Design of Low Power Reduced Complexity Wallace Tree Multiplier using Positive Feedback Adiabatic Logic. In: International Conference on Advanced Computing and Intelligent Engineering. (Vol. 1089, pp. 139-150) 2020.

Copyright

© 2021 Premananda et al.This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. Published By Indian Society for Education and Environment (iSee)