Triple Data Encryption Standard Encryption Engine: A Hardware Approach

Mohd  Marufuzzaman; Noorfazila Kamal; Fazida Hanim Hashim and Mamun Bin Ibne Reaz

doi:10.17485/ijst/2015/v8i30/87232

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Triple Data Encryption Standard Encryption Engine: A Hardware Approach

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2015/v8i30/87232

Year: 2015, Volume: 8, Issue: 30, Pages: 1-7

Original Article

Triple Data Encryption Standard Encryption Engine: A Hardware Approach

Mohd. Marufuzzaman, Noorfazila Kamal, Fazida Hanim Hashim and Mamun Bin Ibne Reaz^*

Universiti Kebangsaan Malaysia, Department of Electrical, Electronic and Systems Engineering, Bangi - 43600, Selangor, Malaysia; [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Cryptography is known as the standard means of rendering a communication private. This research work describes an approach to develop Triple Data Encryption Standard Encryption Engine in FPGA that can be used as a standard device in the secured communication system. The hardware design has been targeted to implement on Altera FLEX10K and FLEX10KE devices. By trading off between the processing time and the security matters the key size of the 3DES encryption engine has been set to 64-bit, which practically provides a considerable amount of security to the communication system. The 3DES encryption engine has made use of 239 units of Logic Cell (LC) with 199MHz. It has been verified that this 3DES encryption engine can perform the 64-bit operation in less than 22.38us